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Evaluation of deep-sub-quarter micron CMOS technology : low noise amplifiers, ESD reliability, and oscillators

Monday, 13 March, 2006 - 15:00
Campus: Brussels Humanities, Sciences & Engineering campus
auditorium P. Janssens
Dimitri Linten
phd defence

Evolutionary power-aware Radio-Frequency (RF) circuit design methods in combination with
the revolutionary improvements in the manufacturability of RFCMOS technologies form the
key for implementing low-power RF front-ends in portable electronic devices.

Sub-90~nm CMOS technology development and circuit design are interlinked. As technology
scaling continues, the inherent reliability issues and the design margins are no longer
independent: to obtain a design for a technology and a technology for a design are the key
issues that need to be considered. To design for a technology means that a designer takes
into account what is feasible in a given technology in a very early stage of the technology
development. Technology for a design on the other hand means that a designer tries to
enhance or to optimize some technology options to obtain a technology that can cope with
more aggressive design challenges. This work addresses both these key issues for the
IMEC 90nm CMOS technology during its development.

A Low-Noise Amplifier (LNA) and a Voltage-Controlled Oscillator (VCO) are present in most
RF front-ends. The design and evaluation of several fully integrated 5 GHz LNAs and VCOs
in 90~nm CMOS are presented in this work. Different process options for the realization of the
integrated inductors (five metal level copper back-end-of-line or Above-IC using wafer-level
packaging techniques) are evaluated experimentally. The use of 90 nm CMOS transistors in
combination with high-quality Above-IC inductors is found to be very suitable for low-power,
high-performance RF design.

However, two major reliability concerns for the final product must be resolved by reliable
circuit design practice: the Hot Carrier Stress (HCS) degradation and the Electrostatic
discharge reliability (ESD). HCS degradation of the RF performance of 90~nm CMOS circuits
can impose a limitation to the use of weak/moderate inversion operation for low-power RF
circuit design. This is investigated on a fully integrated 900 MHz subthreshold LNA realized in
90~nm CMOS. The second reliability concern is circuit degradation or failure due to ESD. The
challenge in ESD protection is that it should not degrade the performance of the circuit to be
protected. Based on ``back-of-the-envelope'' calculations, it is shown that even diodes cannot
be easily implemented to get a sufficient ESD protection solution to protect theRF input of an
LNA in sub-90nm CMOS technologies.

Alternative ESD protection solutions are explored in this work to protect a 5 GHz LNA in a
90nm CMOS technology against ESD stress events and are validated by measurements. An
inductive “plug and play” ESD protection solution is developed for RF LNAs in sub-90nm
CMOS technologies. Benchmarking the ESD-protected LNAs from this work with the open
literature reveals that the “plug and play” inductive ESD-protected LNA with Above-IC
inductors is the first CMOS LNA which achieves both ESD protection level of class 3 HBM
and class 4 MM, while retaining an excellent RF performance at a very low power

To obtain an optimal transistor performance for ESD reliable RF designs, many trade-offs can
still be made during the development of a CMOS technology that is traditionally driven by
digital requirements. Many process variations are possible during the silicon process
optimization. Elevated Source Drain (ES/D) is a process option for the 90nm CMOS
technology node, without any additional mask cost involved. The option provides reliable
silicided contacts for shallow junctions, which is beneficial to control the junction leakage for
digital applications. For RF applications, ES/D can be beneficial, as it reduces the gate sheet
resistance of the MOS transistors. The impact of ES/D on ESD reliability is investigated in
order to see its impact on the ESD reliable design ES/D improves the ESD
robustness of standard ESD protection devices.

As CMOS technology scales towards sub-90nm feature size, silicon real estate becomes very
expensive. Integrated inductors consume a lot of chip area. As Above-IC inductors have a
large distance between the inductor tracks and the lossy silicon, their placement of such
inductors above active circuits would result in area savings and therefore save cost. This is
evaluated experimentally using standalone inductors and a VCO as a circuit demonstrator. It
is found that the inductor performance becomes unpredictable when it is realized on top of a
circuit or active area.

In conclusion, this work has demonstrated a comprehensive investigation to evaluate the
suitability of 90nm CMOS for low-power high performance RF LNA and VCO design, and
addresses the need of technology-aware reliable circuit design.