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Discrete-time receiver topologies for SDR

Tuesday, 17 August, 2010 - 14:00
Campus: Brussels Humanities, Sciences & Engineering campus
Arnd Geis
phd defence

The Software‐Defined‐Radio (SDR) concept is a prospective candidate for answering the ever‐increasing
demand on wireless connectivity. It allows for tuning to each center frequency of interest while
supporting a wide range of channel bandwidths and interference scenarios. The frequency range of
interest for SDR typically extends from the UHF band for terrestrial broadcast, to well over 5 GHz for
WiFi applications. SoC integration in deep sub‐micron CMOS nodes is further necessary in order to reach
higher levels of integration and miniaturization.

The poor analog performance of the active devices in these nodes becomes a burden for the
implementation of analog front‐end and baseband. In contrast to traditional receiver architectures,
discrete‐time receiver implementations, with signal processing in the charge domain, take advantage of
the effects which made scaling so attractive for digital circuitry in the first place. As such, the benefits of
an increased time resolution, reduced switch load, increased capacitance densities and improved
capacitance matching performance in scaled nodes can be maximally exploited. The clock tunable
bandwidth of discrete‐time filters is further attractive for solving the variable bandwidth requirements
of SDR.

In this work, the various challenges of SDR receiver implementations were addressed. A main goal was
to accommodate the high flexibility requirements of SDR by means of sampling and discrete‐time signal
processing. Two different discrete‐time receiver architectures were implemented.

In the first design, sampling was introduced at baseband level and incorporated variable gain, clock
programmable low‐pass filtering and superior anti‐alias performance into a novel sampling stage.

The second receiver implementation performed direct RF‐sampling followed by strong discrete‐time RFband‐
pass filtering and sub‐sampling. Power‐scalable flexible discrete‐time baseband stages allowed for
a maximum trade‐off between bandwidth, noise and power consumption.

The challenge of wide‐tuning range LO‐generation in scaled‐CMOS was addressed. It is demonstrated
that full frequency coverage can be achieved with competitive phase‐noise and power figures.

Finally, programmable LNA solutions were investigated. A low‐area flexible multi‐band, variable‐gain
LNA solution, based on switched multi‐tap inductors, was proposed. The implementation absorbs
significant flexibility in terms of gain, noise, linearity into the front‐end and enables linear multi‐band
operation over the entire frequency range of interest to SDR.